Programmable devices are currently available in several different architectures. Earliest of the programmable devices are the programmable logic array (PLA) devices which comprise a plurality of AND gates programmably connected to a second plurality of OR gates. These devices can generate any combinational logic function, because any combinational logic function can be written as a sum of products, the products being generated in the AND array and the sums being generated in the 0R array. These two level logic devices (one AND level and one 0R level) are simple to program, and it is easy to predict the time delay for generating an output. However, the silicon area needed to calculate a complex logic function can be undesirably large.
More recently, programmable logic devices called field programmable gate arrays or FPGAs have been developed. These devices comprise an array of programmable logic cells which can be interconnected by programmable interconnect lines to generate complex logic functions. In an FPGA device, a function need not be calculated as a two-level sum of products because it is possible to feed the output of any one logic cell to an input of any other logic cell, and thereby form a chain, generating a function which has multiple levels of logic. Thus it is possible to implement complex logic in a smaller physical area.
Several architectures of these field programmable logic devices are available today. The various devices differ in the complexity of a single logic cell. Some manufacturers offer devices having logic cells such as shown in FIG. 1 which are quite small (fine grained architecture). Others offer devices having logic cells such as shown in FIG. 2 which are considerably larger and which handle larger functions within a single logic block (coarse grained architecture).
A small logic cell such as shown in FIG. 1 has the advantage of being able to be completely filled by the logic of a user, and thereby not leave unused logic resources within the cell. It may be possible to generate either combinational or sequential functions from a plurality of small logic cells. However, with fine grained architectures made up of small logic cells, it requires many logic cells to generate a complex logic function. A function which must make use of more than one logic cell must use programmable interconnect line to generate the function. When the signal path passes through resistive programmable elements, the time delay associated with capacitive and resistive interconnect line considerably slows down the response of the sequential function.
The larger celled (coarse grained) logic devices can generate complex functions quickly within a single logic block. However, if the user specifies a set of functions which do not make full use of the rather large logic cell, portions of the logic cell will be unused. Also, some of the fairly large logic cells include separate resources for generating combinational functions and for generating sequential functions. The cell of FIG. 2 is such a cell. If a user wants a circuit which uses many combinational functions and few sequential functions, many sequential resources will be unused. Likewise, if the user wants many sequential functions and few combinational functions, many combinational functions will go unused.
Another significant consumer of silicon faced by designers is that signals must be inverted, and using a configurable cell to generate an inverter consumes resources otherwise available for more powerful functions. Prior efforts have been made to provide dedicated hardware for the invert function. A structure described by Quicklogic in a publication entitled pASIC.TM. 1 Family ViaLink.TM. Technology Very High Speed CMOS FPGAs published May 1991 shows a programmable structure using two-input AND gates which have one inverted input and one non-inverted input. This structure thus gives a choice of applying a signal to the inverted or the noninverted input. Though this solution allows for applying signals to both the inverted and noninverted inputs, when used simply to offer an optional inversion, this solution doubles the number of input lines needed. Thus using the above structure to achieve optional inverters adds considerable silicon area and complexity to a cell.